This invention relates in general to microprocessors and, more specifically, to devices and methods for performing a leading zero calculation with an offset, such as is done in executing a count-consecutive-clear-bits graphics instruction.
As shown in FIG. 1, a conventional device 10 for executing a count-consecutive-clear-bits (cccb) graphics instruction (typically part of a shift operation) includes a leading zero determiner 12 that calculates the number of leading zeros nza in an operand stored in a register rs1. An offset stored in another register rs2is then subtracted from the number of leading zeros nza using an inverter 14 and an adder 16 to arrive at the consecutive clear bits count.
Although the device 10 executes the count-consecutive-clear-bits graphics instruction adequately, the serial nature of the calculation (i.e., determining the number of leading zeros nza, then determining the consecutive clear bits count cccb) makes it slower than desirable.
Accordingly, there is a need in the art for an improved device and method for performing a leading zero calculation with an offset.
In accordance with this invention, an improved device for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits, each associated with a prioritized portion of the operand. Each logic circuit activates an all-zero signal when its respective portion of the operand consists of all zeros, performs a leading zero count on its respective portion of the operand, and generates a leading zero signal by offsetting its leading zero count with a first portion of the offset. Also, a priority encoder generates a signal encoding the priority of the highest priority inactive all-zero signal, and selecting circuitry selects first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal.
Further, generating circuitry generates a no-carryout signal by offsetting the priority encoded signal with a second portion of the offset, generates a carryout signal by offsetting the priority encoded signal with the second portion of the offset and adding one, and selects one of the no-carryout and carryout signals as a second portion of the consecutive clear bits count in accordance with the carryout selector signal.
In other embodiments of this invention, the device described above is incorporated into a processor device, such as a Java processor, and an electronic system.
In a further embodiment, a consecutive clear bits count is performed on an operand with an offset. Specifically, for each of a plurality of prioritized portions of the operand, an all-zero signal is activated when the prioritized portion consists of all zeros, the number of leading zeros in the prioritized portion is counted, and a leading zero signal is generated by offsetting the prioritized portion""s leading zero count with a first portion of the offset. Also, a signal encoding the priority of the highest priority inactive all-zero signal is generated, and first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal are selected as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal. Further, a no-carryout signal is generated by offsetting the priority encoded signal with a second portion of the offset, and a carryout signal is generated by offsetting the priority encoded signal with the second portion of the offset and adding one. Then, one of the no-carryout and carryout signals is selected as a second portion of the consecutive clear bits count in accordance with the carryout selector signal.